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Video-codec cores offer programmability

As more and more devices—from cell phones to surveillance cameras to robots—require video capture, video codecs are becoming almost standard building blocks for SoCs (Systems on Chips). Given the complexity of the computing tasks involved, this area might appear to be one in which specialized hardware will reign unchallenged. But an August 13 introduction from ARC International disputesthat idea.

ARC, a long-standing vendor of customizable RISC cores, has argued for years that properly augmenting a RISC core with SIMD (single- instruction/multiple-data) execution engines enables that core to handle tasks well beyond the range of a CPU alone. The company supports this argument with a family of—for now—fi ve video-codec subsystems, each comprising an ARC 700 RISC core, one or more SIMD units, and specializedhardware.

The advantage of putting the heavy-lifting burden onto programmable hardware is fl exibility. These new ARC VRaptor cores come with supporting software for H.263, H.264, MPEG-4, JPEG, VC-1, and a variety of other codecs. They are adaptable to custom applications, such as the H.264/video-analytics blends that are starting to fi nd use in video surveillance. The disadvantage of the programmable approach, traditionally, has been high power consumption for relatively low performance. And, although advanced processes and aggressive power management have to some degree mitigated this problem, physics issues remain. Accordingly, high-end performance for the cores in this family is H.264 Base Profi le, D1-resolutionencoding at 30 frames/sec.

You must use this benchmark with some care, however, because you can speed things up in a softwaredriven codec by disabling procedures that improve picture quality or reduce bit rate. Conversely, if you turn on all the bells and whistles for excellent picture quality, you can slow down the encoder operation. And power increases with clock frequency and activity, so the more bells and whistles, the more milliwatts the system consumes. For this and other reasons, ARC quotes power-consumption fi gures only under a nondisclosureagreement.

The underlying hardware for the high-end core includes a 700-series RISC CPU core, local memory, a sophisticated DMA arrangement, two SIMD units, and special hardware blocks for motion encoding and for entropy encoding and decoding. The SIMD units are extensions of ARC’s standard SIMD engine, with additional instructions for dealing with video-processing tasks. The specialized units are dedicated hardware blocks with some degree of programmability to accommodate differences in codec requirements. In operation, the RISC core handles sequencing and control, and the SIMD engines take on the high-bandwidth tasks, such as pixel-level transformsand deblocking.

ARC estimates that the high-end 417V core will be slightly larger than 10 mm², including all internal-RAM structures, in TSMC’s (Taiwan Semiconductor Manufacturing Co, www.tsmc.com) 130g process, using Cadence’s (www.cadence.com) layout fl ow and Virage Logic (www.viragelogic.com) libraries. Engineers have extensively simulated the cores and verifi ed them in FPGA emulation, and they are available now. For more on these products, see “Video codecs in software: some refl ections on programmable-hardware approaches,” www.edn.com/070913p1.

ARC, www.arc.com.