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UNDER THE LID ANALOG TEST IS SUDDENLY THE CRITICAL INGREDIENT

AFTER YEARS OF ATTENTION TO DIGITAL-TEST TECHNOLOGY, ANALOG TEST IS EMERGING AS A ROADBLOCK TO COST REDUCTION.

TPG (automatic-test-pattern generation), BIST (built-in self-test), and structural-test techniques have kept digital-test costs nearly constant during the explosion in digital complexity. Without these tools, however, as analog complexity starts to grow rapidly, analog- test cost is growing, too. “AMS [analog and mixed-signal] circuits account for 70% of SoC [System-on-Chip]-test cost and 45% of test-development time, even though they make up a small fraction of the chip complexity,” said Karim Arabi, senior director of engineering at Qualcomm, speaking at a panel on analog-IC test at the ITC (International Test Conference) in Austin, Texas, last November. “There is no ATPG for AMS circuits. There is no practical fault model. And what DFT [design-for-test] and BIST efforts we use are purely custom.” Arabi’s complaint perfectly summarizes the situation.

Three broad strategies for analog test now exist. The first and most traditional approach is characterization—sweeping the inputs through their full allowable range and measuring all the pins to verify each parameter on the data sheet. This approach still dominates—for good reason—in the world of discrete analog components. The second approach, increasingly common in the SoC world, is to use hardware in the chip itself to test the AMS circuitry. The ideal of this school is to achieve something like BIST for AMS: functional blocks that test themselves on command. The third approach is the Holy Grail of AMS test: structural test.

“We need to redefine the problem,” said Craig Force, a test-engineering-platform manager at Texas Instruments, speaking to his fellow ITC panelists. “We don’t want to do parametric test of everything on the data sheet. We want to do the minimum number of tests to prove that the circuit is built right.” Despite years of effort, the goal remains elusive, but hope seems to be slowly returning among some experts.

PROVING THE DATA SHEET

“In our world, we are always fighting for dc precision and for signal fidelity,” says Michael Purtell, product- and test-engineering manager at analog-components vendor Intersil. “You are always asking yourself if you are measuring the part or the equipment. For instance, you look at a spectrum going through an analog-to-digital conversion. What part of what you see is really the device, and what part is due to your measuring technique?”

Welcome to the world of precision analog components, in which the claims on the data sheet define the functional requirements. Because the manufacturer doesn’t know how a customer will use the chip, there is no choice but to verify every number on the data sheet. “We test the minimum/ maximum numbers 100%,” Purtell says. “If something is untestable, we will write it up on the data sheet as ‘typical’.” Such thoroughness leads to long, complex test routines on expensive analog testers with elaborate load boards. Fortunately, however, there is no internal state—at least in purely linear circuits—and it is often sufficient to examine just the pins of a device. “Usually, once you set up the configuration registers for a test mode, you can figure out what you need to know from just the inputs and outputs,” Purtell says.

Such exhaustive testing is not always necessary. “Different markets have different test needs,” says Mark Hemming, director of product development at audiochip vendor Nuvoton. “An automotive customer can be demanding and insist that your test procedure cover everything on the data sheet. For the same part, a commercial customer might just want you to check that the chip works.”

THE SOC SIMPLIFICATION

Although discrete analog components often require full testing of data-sheet parameters, AMS IP (intellectual-property) blocks in SoCs benefit from a defined environment and usually a fixed set of functions. These constraints reduce the test challenge from full characterization to simply verifying some functions. The almostideal case is an IP block that implements a standard interface for which the standard defines the test requirements.

Another considerable simplification for SoC designers is the availability of lots of digital logic. Virtually free gates make it easy to build mode-control registers and to digitally configure the AMS block for test modes: Shorting inputs and enabling loop-back paths are both examples of test modes. The digital wealth also makes possible the latest trend in SoC test: on-chip instrumentation. “We are well into the complexities of implementing on-chip instrumentation,” Force says. “Everyone puts a widget in their SoC.”

The trend has gathered the most momentum in digital blocks in which, Force says, off-the-shelf IP often implements test functions. In more purely linear blocks, test instruments tend to be ad hoc designs. Instruments for each design incur additional design time and die area. These costs don’t mean that you can’t build a signal generator, a voltmeter, and an oscilloscope into your SoC. They do mean that you must do as much of the work as possible in the digital domain and reuse test circuitry for other purposes.

“In an SoC there’s a high comfort level with handling digital signals,” Force says. “Digital is a great medium for passing around data, so anything that we can digitize is good. But you can’t always just hang a 1-bit ADC on a sensitive signal path. Sometimes you are still going to have to resign yourself to carrying out a conventional test.”

One approach to on-chip instrumentation then is to pick up analog signals at key nodes—inputs, outputs, and internal nodes that might not be readily inferable from the outputs—and route them to an ADC. This converter could be a centralized resource if the signals are robust enough to route across the block, or it could be a simple sigma-delta converter, comprising little more than a comparator and a control register, right on the node. Once the converter digitizes the signals, the SoC usually has enough processing power to turn the raw samples into sophisticated measurements.

As for reuse, one example is an SoC’s built-in circuitry that allows customers to perform board-level tests. For instance, if a high-speed-serial-interface specification requires an automatic-calibration mode or a training mode, the hardware that you need in order to implement that function may also be useful in test mode. In this respect, the evolution of signalpath design, as analog designers face the lower voltages and greater process variations at advanced process nodes, is providing resources for test engineers.

“There are two trends here that are really helpful,” says Sanjiv Taneja, vice president for Encounter Test at Cadence. “Increasingly, the analog functions that you have to test at speed are both selfcalibrating and self-adapting. Often, you can reuse those capabilities to implement on-chip test functions.”

AN INSTRUMENTED SERDES

To see this principle in action, Navraj Nandra, director of product marketing for AMS IP at Synopsys, provides a guided tour through a high-speed SERDES (serializer/ deserializer) IP block. The block, an AMS IP function that is available from Synopsys and other IP vendors, serves as a bidirectional interface between a parallel datapath in an SoC and a multigigahertz serial bus that goes to the outside world. A CDR (clock- and data-recovery) circuit lies at the heart of the SERDES. The CDR circuit reconstructs a clock from the incoming signal and then uses that clock to extract raw data bits from the signal. To perform these functions, circuits in the CDR unit must find the phase of the clock that created the data stream, essentially by matching it up with a locally generated clock. In the Synopsys design, that task employs a digitally controlled phase rotator. The phase rotator also performs a second job: By sweeping the phase in test mode and by capturing the output of the CDR circuit with a comparator, designers can build a table of phase versus voltage for an input signal. Sending that data from the chip to a workstation for graphing produces an eye diagram. This debug approach collects the data inside the CDR circuit so that it represents the signal that the SERDES must use to extract the data.

Because most serial-interface standards define minimum signal quality in terms of a polygon that fits into the opening in the eye diagram, the internal tool collects the data that you need to generate a compliance eye mask. “This technique forms the basis for the production test routines, as well,” Nandra says. If you equip an ADC on the output of the CDR circuit with limit registers and if you provide a flexible sample clock to the ADC, you can collect data and send it to external display routines to form, in effect, a sampling oscilloscope (Figure 1). With the scope, you can see not only eye diagrams but also any repetitive waveform that you choose to direct into the ADC’s inputs. Nandra points out that your customers can use these capabilities to measure their designs’ link performance in-system. By simply adding one or two pieces of hardware, the Synopsys designers are getting multiple capabilities for several audiences.

TOWARD ANALOG BIST

The SERDES design employs implementation foresight to permit creative reuse of functional components in test mode, but its techniques are implementationspecific. Another SERDES designer might take a different approach. Designers of a sigma-delta converter, for example, can’t directly apply any of the circuits that the SERDES uses. Although on-chip widgets have rapidly and pervasively proliferated, this growth has not resulted in a library of reusable instruments or in general principles that you can use to automate the design of self-test into analog circuits.

Engineers at the former LogicVision, now a part of Mentor Graphics, have put a lot of thought into this problem. Some of the thinking that Mentor received with the acquisition showed up in the ITC panel discussion. “We are looking for the analog equivalent of scan,” said Stephen Sunter, an engineer with Mentor. “But first we need an accepted fault model. After years of trying, people worry that accuracy is impossible. If that is so, then let’s accept the fact and agree on a model that is adequate for the task. We need to separate the issues of highly accurate characterization from our problem, which is simply to find random defects in our circuits. In the past, we have come up against complex waveforms with huge dynamic ranges, and we have faced complex analyses. But I think we can move forward if we agree on a few techniques. First, use loop-back modes. Second, employ a low-frequency analog bus, controlled by 1149.1, to move analog signals from their sources to an ADC. Third, use a high-frequency serial bus to extract data from a sigma-delta converter. The principle here is to convert voltage into time to manage the huge analog dynamic range and then to do 90% of the work in digital.”

Sunter’s thinking matches what is happening in the SoC area, charts the approach that Synopsys designers used on their SERDES, and describes Nuvoton’s strategy. “To speed parametric testing, you can use an internal analog bus to interrogate analog nodes with high accuracy, but you always wonder if you are accurate enough,” says Nuvoton’s Hemming. “In our market, you worry about cost. So either you try to find circuits that are useful in regular operation, or you design them so that your customers can use them, too.” Hemming illustrates this concept with the rather considerable telephone-line measurement capability in the company’s Pro-X (programmable extended) codecs (Figure 2). It appears that the use of on-chip instrumentation is beginning to coalesce into the sort of general principles that Sunter advocates. We are still a long way, however, from the emergence of a tool that can automatically generate instruments and tests in a design.

ANALOG STRUCTURAL TEST

With all the progress in on-chip instrumentation, a fundamental difference still exists between analog widgets on chips and digital scan or BIST. Engineers manually insert analog instruments into a block as an ad hoc means of measuring its behavior. In contrast, automated tools create synthesized digital scan chains or BIST hardware after analyzing the structure of the logic.

These tools verify the integrity of the structure; they don’t measure the behavior of the logic.

The path from behavioral to structural test runs directly through fault models. If you know what defects can occur on a wafer and you can model the effect of each defect on the circuit, you can deduce how to look in one spot to find a large number of possible problems. In the digital world, ATPG software, scan insertion, and DFT hardware work together to do the minimum number of tests necessary to see all the possible faults. No accepted fault models exist in the analog world, however, so there is no automated way of collapsing an analog network into a minimum set of paths and tests that would prove the structure of the entire circuit.

There is a glimmer of hope—adaptive test—but it comes from statistical, not structural, analysis. Adaptive test collects all the test data as a design runs through production test, applies statistical analysis to all of the data, and identifies tests that detect no unique faults. For instance, a test may find only those faults that another test also finds. If that other test finds additional faults, as well, adaptive- test programs would remove the first test and keep the second. So without fault models or even a knowledge of the circuit topology, adaptive testing can in principle narrow down the test suite until only the minimum necessary number of tests remain.

This scenario is complex, however. It requires a huge amount of data to make confident decisions. You don’t want to eliminate a test only to discover that it was the only way to spot a rare failure. “Most analog parts never reach the kind of volume you’d like for those kinds of decisions,” says Intersil’s Purtell.

Adaptive test, like analog structural test, is still in its childhood. It’s probably not yet possible to estimate the potential for either technique. Someone could propose a powerful set of analog fault models tomorrow, for example, and suddenly make structural approaches much more attractive. But such discoveries are unpredictable. So the industry now faces a problem. Some test techniques are becoming too expensive to use at advanced process nodes. On-chip instruments are becoming more popular but are expensive to design and require verification for accuracy. Both structural and statistical analytical techniques for varying reasons don’t yet help much with analog. AMS test is an important problem with no easy solution on the horizon.