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Xilinx moves Virtex, Spartan forward a generation

 

 

The newest series in Xilinx’ FPGA device families now have a “6” designator; Virtex-6, the flagship series, and Spartan-6, the cost-reduced version. Compared to the company’s “5” generation, capacity is doubled and power consumption halved, the company asserts. The Virtex-6 devices continue to employ the company’s ASMBL architecture and, as with previous series, will come in three variants. Parts with the LXT suffix are for high-performance logic- and DSPintensive applications, and have serial transceivers running at up to 6.5 Gbps; SXT parts are for the most DSP-intensive applications, and have the same serialtransceiver speeds as the LXT; while the HXT parts are for applications that focus on the highest speeds and data bandwidths, with transceivers that will run at up to 11.2 Gbps. Maximum logic density rises to 760k logic cells, maximum onchip memory reaches 38 Mbit of block RAM, and the maximum number of DSP slices is now 2000. As before, the largest devices in this generation will find application in ASIC prototyping, with other chips in the series finding their way into wired and wireless communications, broadcast equipment and aerospace/ defence designs. The Virtex-6 core voltage is now 1.0V, with a low-power option of 0.9V; you can, says Xilinx, expect to see a reduction in power of up to 65% compared to when you implement the equivalent function in a previous-generation part. The two series use a common six-term LUT (look-up-table) FPGA fabric, block RAM structure and DSP-slice architecture. Xilinx has added new FIFO resources to the Virtex-6, which you might use in bridging different clock domains; it also has tri-mode Ethernet—as hard IP (intellectual property)—and a new system monitor capability to report on key chip operating parameters. Among the new features on the Spartan-6 family is a memory controller that handles all DDR standards. The chips will interface to legacy 3.3V logic systems. Spartan-6 parts run at a core voltage of 1.2 or 1.0V.

With these parts, Xilinx CEO Moshe Gavrielov says, FPGAs can make further inroads into what he terms “underserved” custom-chip applications; he contends that—while ASICs are still appropriate for the highest-volume product designs, and while FPGAs already serve a very broad range of lower-volume projects well—there is a growing “gap”. In this sector, you find designs that are moderate-to-high in complexity and production volume, and that can no longer support the overheads of an ASIC design. Gavrielov aims to reduce that gap.

Xilinx, www.xilinx.com.