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Xmos discloses design-flow outline for its event-driven, multithreaded embedded-processor concept

Xmos, the UK-based start-up that is moving towards the launch of a chip product that will offer software-configurable-hardware, has announced that its first—development—silicon is now functional; the company anticipates placing its first product on the market in 2008. Xmos processors will provide parallel processing, software programmability and hardware reconfiguration through software, on an event-driven multithreaded processor array, hosted on a single chip. Founder and chief technology officer David May says that the technology, “provides a meeting point between hardware and software design.” In its latest announcement, the company has provided more insights into how you might use the product. A chip will have some multiple—the test silicon has four—“tiles”, each of which comprises a relatively conventional processor core that supports up to eight concurrent processing threads. Each thread has its own allocation of registers and pointers so that context switches are single-cycle; each tile has its own local memory, out of which each thread operates. Each tile also has its own allocation of I/O ports that are closely coupled to the core. This last point is key to the event-driven nature of the design; throughout, there are no polling mechanisms looking for event flags, and all scheduling is in hardware— threads run, or don’t run, in response to hardware bit values. Thread execution can be driven directly by I/O status, and timers can trigger timerelated events; the eventdriven approach is inherently energy-efficient, the company asserts. Each XCore tile also has an allocation of timing, sychronisation, clockmanagement and locking functions.

You will program each core in a conventional way using C and a compiler; legacy C should recompile without problems, Xmos says. To confi gure communication between threads and tiles, you’ll use a language the company has called XC. While being “C-like”, this language supports timing and concurrency. In XC you declare port and channel parameters such as widths and start/end points, and timing; the XC compiler uses this input to confi gure on-chip routing and switching resources. Embedded software defi nes hardware from a pool of resources as program fl ow requires it; “this is not a ‘C-to-gates’ design fl ow,” the company says. Further, you don’t need any HDL skills to carry out this confi guration aspect of the design— although it will probably fall naturally to those currently on the hardware side of embedded- system design. In a unifi ed design fl ow, you can call XC from within C code, or vice-versa. The ports that you confi gure in XC come in bit widths from one to 32, and have SERDES functions and timing control.

Hardware-thread scheduling guarantees per-thread performance; if you need more performance, you can either run fewer of the available threads of a given core, or sub-divide your task over more threads. In the tool set that Xmos is designing, there will be features that will guide the task of mapping the program fl ow on to threads, but the company appears to believe that an intuitive approach of transferring a conceptual block diagram into processing blocks and communications channels, and thus into C and XC, will work. The tool set will, according to the company, support debugging of operation and identifi cation of bottlenecks if you load too much onto a thread or core. The design process that Xmos sketches begins with partitioning your application into threads, identifying control fl ow, DSP-like processing and I/O processing, which should guide you to a device choice. If C (or C++) and XC have their own compilers, legacy software IP (for example, a protocol stack) is introduced via a linker. Program debug is conventional, and there will be a waveform viewer to confi rm that confi gured hardware is performing as intended.

While believing that its concept will be useful to the full range of embedded processing, Xmos will fi rst focus on consumer-product applications such as set-top boxes, home networking and I/Omanagement functions in mobile devices, where it feels that its combination of fast design turnaround and processing power will make an impact against the cost and design complexity of largescale ASICs and ASSPs.

Many tasks that today’s processors carry out essentially comprise, May says, “a mix of processing tasks that today’s FPGAs address poorly.” He believes that the basic processor-oriented nature of the XCore will effi ciently deal with the former, while you will be able to effectively handle the “detailed timecritical bits” of data streaming and I/O in the XC part of the design fl ow. He also believes that the approach has the capability to outperform dedicated ASSPs, while offering product designers the opportunity to go around the design cycle quickly, make multiple design revisions and add product-differentiating features. XMOS claims “more than ten times the functionality per dollar compared to conventional FPGAs” and believes its product will be costcompetitive with ASIC solutions while being much faster and more fl exible in design.

XMOS, www.xmos.com